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NCP4330 Post Regulation Driver
The NCP4330 houses a dual MOSFET driver intended to be used as a companion chip in AC-DC or DC-DC multi-output post regulated power supplies. Being directly fed by the secondary AC signal, the device keeps power dissipation to the lowest while reducing the surrounding part count. Furthermore, the implementation of a N-channel MOSFET gives NCP4330-based applications a significant advantage in terms of efficiency.
Features
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8 8 1 4330D A L Y W SO-8 D SUFFIX CASE 751 1 = Device Number = Assembly Location = Wafer Lot = Year = Work Week 4330D ALYW
* * * * * * * * *
Undervoltage Lockout Thermal Shutdown for Overtemperature Protection PWM Operation Synchronized to the Converter Frequency High Gate Drive Capability Bootstrap for N-MOSFET High-Side Drive Over-Lap Management for Soft Switching High Efficiency Post-Regulation Ideal for Frequencies up to 400 kHz This is a Pb-Free Device
Typical Applications
* ATX 3V3 Post-Regulation * Offline SMPS with MAGAMP Post-Regulation * Multi-Outputs DC-DC Converters
VDD VDD Vref, UVDth Band-Gap Level Shifter AR2 HS_DRV
Buffer
PIN CONNECTIONS
HS_DRV 1 BST 2 RST 3 BST C_ramp 4 (Top View) 8 GND 7 LS_DRV 6 VDD 5 I_ramp
VDD Undervoltage Detection (UVD high if VDD < 4.9 V) RST RESET Block U4 + - Iramp VDD Current Mirror
UVD HS_DRV and LS_DRV low
ORDERING INFORMATION
U1 INVERTER Device NCP4330DR2G Package SO-8 (Pb-Free) Shipping 2500 / Tape & Reel
U3 VDD AR3 LS_DRV
Buffer
2.5 V/1.5 V C_ramp I_ramp Iramp
OR Hysteresis Comparator
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
GND
Figure 1. Block Diagram
(c) Semiconductor Components Industries, LLC, 2005
1
August, 2005 - Rev. 0
Publication Order Number: NCP4330/D
NCP4330
Converter Winding Voltage
0V
Time
Synchronization Signal
2.55 V
Time Internal RESET Signal Time
C_ramp Voltage
0V
VrefH VrefL
Time High-Side Driver (referenced to HS MOSFET source) Time Low-Side Driver
100 ns delay
100 ns delay
Time
Figure 2. Timing Diagram(s)
DETAILED PIN DESCRIPTION(S)
Pin Number 1 2 Name HS_DRV BST Function "HS_DRV" is the gate driver of the high-side MOSFET. "BST" is the bootstrap pin. A 0.1 mF to 1.0 mF ceramic capacitor should be connected between this pin and the node that is common to the coil and the two MOSFET. The "BST" voltage feeds the high-side driver ("HS_DRV"). The "RST" pin resets the C_ramp voltage in order to synchronize the post-regulator free-wheeling sequence to the forward converter demagnetization phase. The capacitor connected to the C_ramp pin enables to adjust the delay in turning on the high-side MOSFET (in conjunction with "I_ramp" current). The "I_ramp" pin receives a current supplied by a regulation means. This current adjusts the delay after which the high-side MOSFET is turned on. By this way, it modules the high-side MOSFET on time in order to regulate the output voltage. "VDD" is the power supply input. A 0.1 mF to 1.0 mF ceramic capacitor should be connected from this pin to ground for decoupling. "LS_DRV" is the driver output of the low-side MOSFET gate. Ground.
3 4 5
RST C_ramp I_ramp
6 7 8
VDD LS_DRV GND
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NCP4330
MAXIMUM RATINGS
Symbol BST RST C_ramp I_ramp VDD RqJA TJ TJmax TSmax TLmax Bootstrap Input Reset Input Timing Capacitor Node (Note 1) Regulation Current Input (Note 1) Supply Voltage Thermal Resistance Operating Junction Temperature Range (Note 2) Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 s) Rating Value -0.3, +40 -0.3, +5.0 -0.3, VrampHL -0.3, Vcl -0.3, +20 180 -40, +125 150 -65 to +150 300 Unit V V V V V C/W C C C C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. VrampHL and Vcl are the internal clamp levels of pins 4 and 5 respectively. 2. The maximum junction temperature should not be exceeded.
ELECTRICAL CHARACTERISTICS (VDD = 10 V, VBST = 25 V, TJ from -25C to +125C, unless otherwise specified.)
Symbol High-Side Output Stage VHS_H VHS_L Isource_HS Isink_HS tr-HS tf-HS TLS-HS High-Side Output Voltage in High State @ Isource = -100 mA High-Side Output Voltage in Low State @ Isink = 100 mA Current Capability of the High-Side Drive Output in High State Current Capability of the High-Side Drive Output in Low State High-Side Output Voltage Rise Time from 0.5 V to 12 V (CL = 1.0 nF) High-Side Output Voltage Fall Time from 20 V to 0.5 V (CL = 1.0 nF) Delay from Low-Side Gate Drive Low (High) to High-Side Drive High (Low) 22.5 - - - - - - 23.5 0.9 0.5 0.75 25 25 100 - 1.5 - - - - - V V A A ns ns ns Characteristic Min Typ Max Unit
Low-Side Output Stage VLS_H VLS_L Isource_LS Isink_LS tr-LS tf-LS Low-Side Output Voltage in High State @ Isource = -500 mA Low-Side Output Voltage in Low State @ Isink = 750 mA Current Capability of the Low-Side Drive Output in High State Current Capability of the Low-Side Drive Output in Low State Low-Side Output Voltage Rise Time from 0.5 V to 7.0 V (CL = 2.0 nF) Low-Side Output Voltage Fall Time from 9.5 V to 0.5 V (CL = 2.0 nF) 7.4 - - - - - 8.2 1.3 0.5 0.75 25 25 - 1.7 - - - - V V A A ns ns
Ramp Control Icharge C_ramp Current @ Ipin5 = 100 mA @ Ipin5 = 1.5 mA Pin5 Clamp Voltage @ Ipin5 = 1.5 mA Ramp Control Reference Voltage, Vpin4 Falling Ramp Control Reference Voltage, Vpin4 Rising Ramp Voltage Maximum Value @ Ipin5 = 1.5 mA Ramp Voltage Low Voltage @ Ipin5 = 1.5 mA mA 90 1400 0.7 1.3 2.25 3.2 - 102 1590 1.4 1. 5 2.5 3.6 - 110 1800 2.1 1.7 2.75 4.2 100 V V V V mV
Vcl VrefL VrefH VrampHL VrampLL
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NCP4330
ELECTRICAL CHARACTERISTICS (continued) (VDD = 10 V, VBST = 25 V, TJ from -25C to +125C, unless otherwise
specified.) Symbol VDD Management UVDH UVDL HUVD IDD1 IDD2 IDD3 Reset Block Vrst_th Hrst Treset Ireset Vcl-neg Reset Block Threshold Reset Comparator Hysteresis Reset Pulse Duration C_ramp Pin Average Current, a 200 kHz, 50% duty cycle Pulse Generator being applied to reset pin and 1.0 V to pin 4 (C_ramp) and @ Iramp = 0 Negative Clamp Level @ Ipin3 = -2.0 mA 2.2 0.8 - 0.3 -0.5 2.5 1.0 250 0.7 -0.3 2.8 - 500 - 0 V V ns mA V Undervoltage Lockout Threshold (VDD Rising) Undervoltage Lockout Threshold (VDD Falling) Undervoltage Lockout Hysteresis Consumption: @ Vpin4 = 3.0 V and Ipin5 = 500 mA @ Vpin4 = 0 V and Ipin5 = 500 mA @ Vpin4 Oscillating 0 to 3.0 V at 200 kHz, Ipin5 = 500 mA 5.2 4.9 400 - - - 5.8 5.2 600 13 7.0 10 6.4 5.5 - 20 12 15 V V mV mA Characteristic Min Typ Max Unit
Temperature Protection Tlimit Htemp Thermal Shutdown Threshold Thermal Shutdown Hysteresis - - 150 50 - - C C
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NCP4330
18 9.0
16
8.2
IDD1 (mA)
12
IDD2 (mA) 25 TEMPERATURE (C) 125
14
7.4
6.6
10
5.8
8 -25
5.0 -25
25 TEMPERATURE (C)
125
Figure 3. IDD1 Consumption vs. Temperature
Figure 4. IDD2 Consumption vs. Temperature
14 13 12 IDD3 (mA) 11 10 9 8 -25
6.0
5.9 UVD_H (V) 25 TEMPERATURE (C) 125
5.8
5.7
5.6
5.5 -25
25 TEMPERATURE (C)
125
Figure 5. IDD3 Consumption vs. Temperature
Figure 6. Undervoltage Lockout Upper Threshold vs. Temperature
5.22
700 660
5.20 H_UVD (V) 125 620 580 540 5.16 500 5.14 -25 460 -25 UVD_L (V)
5.18
25 TEMPERATURE (C)
25 TEMPERATURE (C)
125
Figure 7. Undervoltage Lockout Lower Threshold vs. Temperature
Figure 8. Undervoltage Lockout Hysteresis vs. Temperature
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NCP4330
108 106 104 Ipin4 (mA) 102 100 98 96 -25 1540 Ipin4 (mA) 25 TEMPERATURE (C) 1620 1700
1660
1580
125
1500 -25
25 TEMPERATURE (C)
125
Figure 9. Pin4 Charge Current vs. Temperature (@ Ipin5 = 100 mA)
Figure 10. Pin4 Charge Current vs. Temperature (@ Ipin5 = 1.5 mA)
1.8
3.75 3.70 3.65 3.60 3.55 3.50 3.45 -25
1.6 VrampHL (V) 25 TEMPERATURE (C) 125
Vcl (V)
1.4
1.2
1.0
0.8 -25
25 TEMPERATURE (C)
125
Figure 11. Pin5 Clamp Voltage vs. Temperature
Figure 12. Pin4 Clamp Voltage vs. Temperature
1.60
2.60
1.58
2.58
1.54
VrefH (V) 125
VrefL (V)
1.56
2.56
2.54
1.52
2.52
1.50 -25
25 TEMPERATURE (C)
2.50 -25
25 TEMPERATURE (C)
125
Figure 13. Ramp Control Reference Voltage vs. Temperature (Vpin4 falling)
Figure 14. Ramp Control Reference Voltage vs. Temperature (Vpin4 rising)
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NCP4330
2.60 1.00
2.55 Vrst_th (V) Hrst (V) 25 TEMPERATURE (C) 125
0.99
2.50
0.98
2.45
0.97
2.40 -25
0.96 -25
25 TEMPERATURE (C)
125
Figure 15. Reset Threshold vs. Temperature (Vpin3 rising)
Figure 16. Reset Comparator Hysteresis vs. Temperature
350
1.0 0.9 0.8 0.7 0.6
300 T_reset (ns) Ireset (mA) 25 TEMPERATURE (C) 125
250
200
150
0.5 0.4 -25
100 -25
25 TEMPERATURE (C)
125
Figure 17. Reset Time vs. Temperature
Figure 18. Pin4 Average Sink Current vs. Temperature (@ f = 200 kHz, Vpin4 = 1 V and Iramp = 0 A)
2.45
-0.20
-0.24 Vcl_neg (V) VHS_H (V) 25 TEMPERATURE (C) 125
24.0
-0.28
23.5
-0.32
-0.36
23.0
-0.40 -25
22.5 -25
25 TEMPERATURE (C)
125
Figure 19. Pin3 Negative Clamp Voltage vs. Temperature (@ Ipin3 = -2 mA)
Figure 20. High-Side Drive Voltage vs. Temperature (high state, Isource = -100 mA, @ Vbst = 25 V)
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NCP4330
1.1 1.0 TLS_HS (ns) 25 TEMPERATURE (C) 125 0.9 VHS_L (V) 0.8 0.7 0.6 0.5 -25 160 150 140 130 120 110 100 -25
25 TEMPERATURE (C)
125
Figure 21. High-Side Drive Voltage vs. Temperature (low state, Isink = 100 mA, @ Vbst = 25 V)
Figure 22. Low Side to High Side Delay vs. Temperature
9.0 8.8
1.35
1.30 8.5 VLS_H (V) 8.3 8.0 1.20 7.8 7.5 -25 1.15 -25 VLS_L (V) 25 TEMPERATURE (C) 125 1.25
25 TEMPERATURE (C)
125
Figure 23. Low-Side Drive Voltage vs. Temperature (high state, Isource = -500 mA, @ VDD = 10 V)
Figure 24. Low-Side Drive Voltage vs. Temperature (low state, Isink = 750 mA, @ VDD = 10 V)
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NCP4330
DETAILED OPERATING DESCRIPTION Introduction The NCP4330 is designed for forward, multiple output power supplies using synchronous rectification. One output is traditionally regulated thanks to a regulation arrangement that modulates the forward converter duty cycle. The other outputs are regulated by a dual MOSFET arrangement driven by the NCP4330. The high-side MOSFET turns on during one part of the forward converter on-time, while the low-side power switch is ON for the rest of the period (free wheeling). The sequencing of the switching phases, includes over-laps that result in only one hard switching (high-side turn on). The three other transitions are soft for an optimum efficiency. The synchronous rectification enables to keep a Continuous Conduction Mode (CCM) operation whatever the load is, as this technique allows to send back some energy towards the input (light load conditions). In Continuous Conduction Mode (CCM), the forward duty cycle is simply given by the following equation:
df + (ns Vout1 np) * Vin
Pin 5 current is internally mirrored in order to charge the Cramp capacitor. An internal comparator (1.0 V hysteresis) detects when the capacitor voltage exceeds the 2.5 V internal reference. At that moment, the low-side MOSFET turns off. 100 ns later (typically), the high-side MOSFET switches on and keeps on until (following the turn off of the forward converter power switch) a RESET signal is applied to pin 3. At that time, an internal switch grounds the Cramp pin and abruptly discharges the Cramp capacitor. As a consequence, the internal comparator turns low and forces the low-side MOSFET on. The high-side MOSFET turns off 100 ns later. During the 100 ns during which both high and low side MOSFETs are on, the MOSFET Q1 of the application schematic is off and no energy can then be drawn from the converter transformer. Therefore, these 100 ns should not be considered as a part of the high-side MOSFET conduction time which can be computed as follows:
ton_HS + Tsw * tRST * tLS, HS * tcharge
where: - df is the forward duty cycle, - ns/np is the transformer turn ratio (np: primary number of turns, ns: secondary number of turns), - Vin is the forward converter input voltage, - Vout1 is the main output voltage of the forward converter. The post-regulated output voltages are given by the following equation:
n Voutn + dn * ns * Vin, p
where: - Tsw is the forward switching period, - tRST is the Cramp reset time during which the capacitor is kept grounded, - tLS,HS is the delay between the low-side turn off and the high-side switch on. During this time, 100 ns typically, the two drivers are in low state, - tcharge is the time necessary to charge the C_ramp capacitor up to the 2.5 V reference voltage. Given that:
tcharge + Cramp * Vref Iramp
where dn is the duty cycle of the post-regulator n, with dn < df since (ns*Vin/np) is available only during the forward converter on-time. Post-regulated output voltages are then necessarily lower than the main regulated one. Sequencing and Regulation Block The timing diagram of page 2 portrays the phases sequencing. Typically, a regulation arrangement injects a current into pin 5, in order to adjust the high-side MOSFET duty cycle.
where: - Cramp is the capacitor connected to the C_ramp pin, - Iramp is the current injected into the I_ramp pin, - Vref is the 2.5 V reference voltage, the following equation dictates the high-side MOSFET duty cycle:
don_HS + 1 * tRST ) tLS, HS ) Tsw
Cramp*Vref Iramp
The following curve gives don_HS versus the current Iramp in the following conditions: 400 kHz switching frequency, 250 ns reset pulse duration, 100 ns switching delay (between LS and HS), 100 pF Cramp capacitor.
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NCP4330
100
75 D (%)
free wheeling operation continues (refer to application schematic). However, such a situation should occur only during transient phases. Should this state occur too frequently, an excessive heating of the Q2 switch could be produced.
70 60
50
25 D (%)
50 40 30 20
0 0 0.5 1.0 1.5 2.0 2.5 I_ramp (mA)
Figure 25. High-Side MOSFET Duty Cycle vs. I_ramp
Conditions: Switching Frequency: 400 kHz, Reset Pulse Duration: 250 ns, Switching Delay (between LS and HS): 100 ns, Cramp = 100 pF.
10 0 0
0.1
0.2
0.3 0.4 I_ramp (mA)
0.5
0.6
One can note that the duty cycle increases when the I_ramp current increases. The duty cycle is zero if the I_ramp current is below about 110 A. The duty cycle is limited to about 81% mainly by the reset time and the 100 ns delay that all together represent 14% of the period. In a 100 kHz application, the relative impact of these times would be reduced and the maximum duty cycle would be higher (in the range of 92%). In fact, the high-side on-times are useful only during the forward on-times. Finally, if the duty cycle of the forward converter is less than 80%, one can consider that the useful post regulator duty cycle can vary between 0 and 100%. It can also be noted that the HS MOSFET can be turned on while the forward power switch is off, the forward free-wheeling MOSFET (Q2) is on and then no voltage is applied to the post-regulator. This is not an issue since the MOSFETs Q2 and Q3 derive the L2 coil current so that the
Figure 26. HS MOSFET Duty Cycle vs. I_ramp (zoom)
RESET Block The "reset" pin should receive the free-wheeling drive signal of the forward (refer to application schematic). When this voltage exceeds the reset block threshold (2.55 V typically), the C_ramp capacitor is grounded by an internal switch for about 250 ns and the low-side MOSFET is turned on. The circuit is then initialized for a new cycle. The voltage that is applied to the "reset" pin, may be negative during one part of the period. The NCP4330 incorporates a negative clamp system to avoid that too negative voltages on the pin may cause carriers injection within the die. The negative clamp acts to force a minimum voltage of about -0.3 V in conjunction with the external resistor R3. It features a current capability of about 2.0 mA.
C_ramp C
VDD Negative Clamp
RESET Pin Voltage
Reset signal R3 RST pin GND 2.55 V/ 1.55 V - +
VDD
Vdelay 1 250 ns 2 AND
Ctrl 3
Q? NPN
Vdelay
Ctrl 250 ns
HYST COMP
To HS and LS drivers
Figure 27. Reset Block
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NCP4330
Low-Side Driver Stage The timing diagram of page 2 portrays the sequencing driven by the NCP4330. The low-side drive is controlled by an internal comparator that compares the C_ramp voltage to the internal reference 2.5 V (1.0 V hysteresis). When the C_ramp exceeds the 2.5 V reference, the comparator turns high forcing the low-side MOSFET off. 100 ns later, the high-side MOSFET switches on. When a reset signal is applied to the reset pin, the C_ramp capacitor is grounded. As a consequence, the internal comparator turns low and forces the low-side MOSFET on. 100 ns later, the high-side MOSFET switches off. The low-side drive is designed to drive on and off a 25 nC gate charge power MOSFET, in 25 ns typical.
1. Low-Side MOSFET Turn On:
In nominal operation, the body diode is already ON when the low-side MOSFET turns on. The energy Qg to be supplied is then approximately half the energy necessary if the drain source voltage was high. The necessary current capability is then:
Ils * on + 1 * 25 nC , that is 500 mA. 2 25 ns
80.0
0
6.50
16.0
40.0
Vin vin1 lind i(l1)
60.0 v(vsn) in volts
-80.0 i(l1) in amps
4.50
12.0
20.0 ls_drv in volts ls_drv 0 LS_DRV
vin1 in volts
40.0
-160
2.50
irl in amps
8.00
irl 20.0 -240 500 M 4.00 -20.0 IQ
0
-320
-1.50
0
-40.0
VQ v(vsn) 4.5010 M 4.5015 M 4.5020 M Time in Secs 4.5025 M 4.5030 M
Figure 28. Low-Side MOSFET Turn ON
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NCP4330
2. Low-Side MOSFET Turn Off:
The high-side MOSFET turns on about 100 ns after the low-side one is switched off. During this time when both switches are off, the body diode of the low-side MOSFET derives the inductor current (in nominal load condition, when the coil current is positive, i.e., it flows toward the output). As a result, the LS MOSFET turns off while its drain-source voltage keeps around zero due to its body diode activation. Again, the energy Qg to be supplied is then approximately half its value if the drain source voltage was high. The necessary current capability is then:
Ils * off + 1 * 25 nC , that is 500 mA. 2 25 ns
High dV/dt occur in the application. When the high-side MOSFET turns on, the drain-source voltage of the low-side MOSFET sharply increases, producing a huge current through the Crss capacitor. This current may produce some parasitic turn on of the LS MOSFET if the driver impedance is not low enough to absorb this current without significant increase of the driver voltage. The driver current capability has then been increased to 750 mA so that it can effectively face a 30 V variation in 10 ns with a MOSFET exhibiting a 250 pF Crss.
vin1
80.0
0
6.50
16.0
40.0 Vin
60.0 v(vsn) in volts
-80.0 i(l1) in amps
4.50
12.0
20.0 ls_drv in volts
lind
i(l1)
vin1 in volts
irl in amps
LS_DRV 0 ls_drv
40.0
-160
2.50
8.00
20.0
-240
500 M
4.00
-20.0 IQ v(vsn) VQ irl
0
-320
-1.50
0
-40.0
4.4990 M
4.4995 M
4.5000 M Time in Secs
4.5005 M
4.5010 M
Figure 29. Low-Side MOSFET Turn Off
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NCP4330
High-Side Driver Stage The high-side turn on (turn off) is 100 ns delayed behind the low-side turn off (turn on). The high-side drive is designed to drive on and off 12.5 nC gate charge power MOSFET, in 25 ns typical.
1. High-Side Turn On:
As portrayed by in figure 30, the high-side turn on is a "hard" switching (large dV/dt and dI/dt). The necessary current capability is then:
Ihs * on + 12.5 nC , that is 500 mA. 25 ns
vin1
8.00
80.0
0
16.0
40.0 Vin i(l1)
4.00 v(vsn) in volts
60.0 i(l1) in amps
-80.0
12.0
20.0 ls_drv in volts
lind
hs_drv HS_DRV 0
vin1 in volts
0
40.0
-160
irl in amps
8.00
ihs -4.00 20.0 -240 4.00 -20.0 VQ -8.00 0 -320 0 -40.0 IQ vdshs
4.4990 M
4.4995 M
4.5000 M Time in Secs
4.5005 M
4.5010 M
Figure 30. High-Side MOSFET Turn On
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NCP4330
2. High-Side Turn Off:
The high-side MOSFET turns in a very soft way (no current, no voltage). The turn off drive is in fact designed to face the high dV/dt that occurs when the MOSFET Q1
abruptly turns on. The current capability has been set to 750 mA so that a 30 V variation in 10 ns cannot parasitically switch on a high-side MOSFET exhibiting a 250 pF Crss.
vin1
8.00
80.0
0
16.0
40.0
Vin
lind 4.00 v(vsn) in volts 60.0 i(l1) in amps -80.0 12.0 20.0 ls_drv in volts
i(l1)
hs_drv HS_DRV 0
vin1 in volts
0
40.0
-160
irl in amps
8.00
IQ -4.00 20.0 -240 4.00 -20.0 VQ -8.00 0 -320 0 -40.0
ihs
vdshs
4.5010 M
4.5015 M
4.5020 M Time in Secs
4.5025 M
4.5030 M
Figure 31. High-Side MOSFET Turn Off 3. Input Voltage Limitation:
Traditional high-side drivers turn off the MOSFET they control, by forcing nearly 0 V between gate and source. The NCP4330 high-side stage is not referenced to the MOSFET source but to ground, and the HS MOSFET is forced off by grounding its gate. This technique that saves the pin that is traditionally connected to the MOSFET source, allows a robust turn off of the power switch. In effect, the low-side MOSFET that is ON when the high-side is off, forces the High-side MOSFET source to approximately 0 V. However the high-side MOSFET turn on is preceded by a 100 ns phase during which both the low-side and high-side power switches are off. During this 100 ns phase, the drain source voltage of the low-side MOSFET may get high, given that in light load operation, the L2 coil current may get negative and flow from the load toward the input through the HS MOSFET body diode. In this case, the gate source voltage of the high-side MOSFET becomes negative and substantially equal to the input voltage amplitude of the post-regulator in absolute value.
Therefore, the maximum value of the pulsed input voltage should be chosen lower than the maximum source-gate voltage the HS MOSFET can sustain. Traditional MOSFET Vgs maximum ratings are generally +/-20 V. Therefore, with this kind of MOSFETs, the input voltage must keep below 20 V (possible spikes being included). Undervoltage Lockout An undervoltage lockout comparator is incorporated to guarantee that the device is fully functional before enabling the output stages. The NCP4330 starts to operate when the power supply VDD exceeds 5.8 V. A 600 mV hysteresis avoids that some noise on the VDD might produce some erratic turns on and off of the device. When the NCP4330 detects an undervoltage lockout condition, it keeps both the high-side and low-side drivers in low state. The undervoltage lockout has a 4.9 V minimum threshold (falling). As a consequence, around 3.4 V are available on the driver outputs to force on the MOSFET. Such a level allows to properly drive most MOSFETs.
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DIODE_OPTO Input Voltage L1 INDUCTOR R1 Q2 C1 Q1 Buffer VIN C5 CAP S2 SW DIODE C1 VDD (6) VDD Band-Gap
VDD Undervoltage Detection (UVD high if VDD<4.9 V)
VCC LOAD
T1 TRANSFO +
OPTO1 R5 TL431 R6
C6
S1 SW R2 VM 0V
R7 RES1 Forward Control Circuitry
Q3 R4
L2
Vout INDUCTOR1 10k + C4 LOAD
OPTO1 NPN-PHOTO Buffer VDD D2
MC33152
Active Clamp
(2) BST Vref, UVDth AR2 Buffer Level Shifter UVD HS_DRV and LS_DRV low (1) HS_DRV
C3 CAPACITOR C5 CAP
BST CAP
NCP4330
APPLICATIONS INFORMATION
Figure 32. Typical Application
The maximum value (VM) of the pulsed input voltage (VIN) must be kept lower than the maximum source-gate voltage the HS MOSFET can sustain
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T2 TRANS1 C7 CAPACITOR R3 RST (3) RESET Block U4 C_ramp (4) I_ramp (5) Iramp Iramp 2.5V / 1.5V + - C2 CAP Hysteresis Comparator VDD Current Mirror GND (8) U? OR D1 DIODE Vout Regulation Block
15
U3 INVERTER
VDD
AR3 Buffer
(7) LS_DRV
Q4
NCP4330
If the input voltage may exceed the maximum source-gate voltage the HS MOSFET can sustain, an intermediary stage should be inserted between the NCP4330 and the HS MOSFET. Figure 33 presents a solution consisting of a diode, a PNP and a resistor (in the range of 500 W). The HS MOSFET is normally turned on through the diode while the PNP Q2 enables to drive the MOSFET between gate and source at turn off.
VIN D4
HS MOSFET
R9 Q2 NCP4330 1 BST 2 RST 3 C_ramp 4 8 LS MOSFET 7 6 VDD 5 I_ramp
Figure 33.
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NCP4330
PACKAGE DIMENSIONS
SO-8 D SUFFIX CASE 751-07 ISSUE AG
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
-X- A
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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17
NCP4330
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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18
NCP4330/D

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